The present invention may be employed in any electronic system in which there is a need for sequential addressing of memory locations in time with pulses received from a clock. The technique of serial addressing a memory array is very widely used in a wide variety of electronic products. Serial addressing is commonly achieved using binary counters, shift registers, ring counters etc., whose basic building blocks are D-latches, J-K master-slave flip-flops, and similar circuits. Many electronic circuit text books, as well as integrated circuit manufacturers' technical literature, provide specifications and technical details of the various methods of building such circuits.
Five text books are noted, in particular, that explain known "counting" circuits which may be used for sequential addressing. The five above-referenced text books are: (1) Meiksin, Z. H., Thackray, P.C. Electronic Design With Off-The-Shelf Integrated Circuits, 2nd Ed., pp.336-337; (2) Millman, J., Halkias, C. C., Integrated Electronics: Analog and Digital Circuits and Systems, pp. 630-631; (3) Comer, D. J., modern Electronic Circuit Design, pp. 416-419; (4) Hughes, F. W., Illustrated Guidebook to Electronic Devices and Circuits, pp. 348-351; and (5) Lenk, J. D., Digital Integrated Circuits, pp. 332-335, each of which is hereby incorporated herein by reference.
Addressing of memory locations that contain pixel information for a video display is one particular application in which sequential addressing may be required. Sequential addressing is useful in video applications because it permits sequential selection of the pixel rows and columns that make up the display screen. Sequential scanning of the memory locations for screen information can be carried out in conjunction with the scanning of an electron source across the screen of the display.
Heretofore, sequential addressing of memory locations containing pixel information has been achieved using a series of standard J-K master-slave or other flip-flop devices. While such devices do enable the required sequential addressing to be carried out, they do so at the expense of considerable density and power consumption penalties.
For example, FIG. 1 shows a known dynamic shift register which may be used for sequential addressing applications. The shift register does not use the J-K master-slave flip-flop, which is the popular work horse of the industry for this type of application. Because the shift register does not use J-K flip-flops, it uses fewer devices per stage as compared with several other circuits described in the text books listed above. Even though the shift register does not use J-K flip-flops, it still uses six active devices (plus two parasitic capacitors) per stage. Furthermore, in order to use the shift register as a walking `1` circuit (for sequential addressing of a video memory), its input has to be loaded with a leading "1" followed by a continuous string of zeros. The alternative is to use a standard J-K Master Slave flip-flop or some other (e.g., D-type) flip-flop to build a shift register/binary counter. Each, however, requires a large number of active devices per stage and consumes much more power. The density is also poor because of the high device count per stage.
Examples of the prior art are provided by the following U.S. Patents, U.S. Pat. No. 3,579,273, Dynamic Shift Register (Harold D. Cook) discloses a general purpose dynamic shift register wherein the input data can be a series of digital "1"s and "0"s in any random sequence; the sequence being repeated at the successive stages of the register with precise time lags. It can be used as a walking "1" circuit if the first input is a "1" and the subsequent inputs are "0". However, it does not provide bidirectionality and does not include means for resetting all the stages to "0" to initiate a new cycle. The two embodiments shown in the '273 patent use four and three transistors per stage plus storage capacitors. An extra transistor would be required per stage to include the reset feature.
U.S. Pat. No. 3,643,106, Analog Shift Register (Berwin et al.) discloses an analog/digital shift register using two transistors and two capacitors per stage. In addition to the input data pulse, it needs four more input clock pulses, identified as K1, K2, G1 and G2 and a couple of "batteries" B1 and B2 in the preferred embodiment (FIG. 1). Embodiments of the invention do not need the input data pulse and use only two clock pulses.
U.S. Pat. No. 3,676,711, Delay Line Using Integrated MOS Circuitry (Ahrons) discloses a "bucket brigade" type of delay line. The delay line circuit can also be used as a shift register or a walking "1" circuit. This circuit, however, requires six transistors and a capacitor per half-stage and is therefore far more complex and expensive as compared with the circuit of the invention.
U.S. Pat. No. 3,708,690, Shift Register (Paivinen) discloses a multi-phase shift register using only "half" circuit per stage, as opposed to a pair of "half" circuits used in a conventional shift register. This is made possible by using an additional "half" circuit per column which is "empty" and is linked up dynamically with successive stages to serve momentarily as the missing second "half" of the stage. However, each "half" circuit still uses three transistors and a storage capacitor; and each stage of the shift register requires a corresponding dedicated stage in an accompanying ring counter plus several peripheral circuits. The circuit is far more complex than the circuit disclosed in the present invention.
U.S. Pat. No. 3,789,239, Signal Boost for Shift Register (Heeren) discloses a type of shift register used to "increase slightly the voltages at the capacitor nodes in order to enhance the operation of the shift register". The walking "1" circuit of the invention does not require this type of enhancement and, therefore, distinguishes from the '239 patent.
The sequential addressing circuit of the present invention provides significant improvement in the density and power of the circuit as compared with the above-referenced circuits. In light of the industry wide desire of minimizing display bulk, weight, and power consumption, there is a need to improve upon the previously used sequential addressing circuits.
The circuit of the invention uses fewer active devices per stage and consumes less power as compared with known counting circuits. Also, the circuit of the invention is sufficiently compact that it improves the packing density of the array in most applications.